1. Field
Various embodiments of the present invention relate to an electronic circuit design technology, and more particularly, to an image sensing device.
2. Description of the Related Art
Image sensing devices capture images using the photosensitive properties of semiconductor materials. Image sensing devices can be classified into charge coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. The CMOS image sensing devices allow for analog circuits and digital control circuits to be realized on a single integrated circuit (IC).
An image sensing device includes an analog-to-digital converter (ADC) to convert an analog signal (i.e., a pixel signal outputted from a pixel array) into a digital signal. The ADC generally uses a clock when converting the analog signal to the digital signal. The operation speed and power consumption of the ADC have a direct influence on the performance of the image sensing device.
Recently, to increase the operation speed and reduce power consumption of the ADC, image sensing devices have been adopting a double data rate (hereinafter referred to as “DDR”) scheme and, by extension, a quad data rate (hereinafter referred to as “QDR”) scheme. The DDR scheme uses a single clock signal having a frequency that is half of a source clock signal, and the QDR scheme uses two clock signals having a frequency that is a quarter of the source clock signal. Accordingly, the power consumption of the DDR scheme is substantially the same as that of the QDR scheme. However, the QDR scheme has an advantage in that the QDR scheme uses an internal clock signal that has a lower frequency than that of the DDR scheme.
FIG. 1 is a block diagram illustrating a conventional image sensing device 100 on the basis of the QDR scheme.
Referring to FIG. 1, the image sensing device 100 includes a control block 110, a ramp voltage generation block 120, a frequency division block 130, a pixel array 140, and a pixel signal processing block 150.
The control block 110 generates operation control signals ROW_CTRLs for controlling operations of the pixel array 140 by rows for each unit row time.
The ramp voltage generation block 120 generates a ramp voltage VRAMP having a predetermined ramp up/down pattern for each unit row time. For example, the ramp voltage generation block 120 generates the ramp voltage VRAMP increasing or dropping by a predetermined voltage for each unit row time.
The frequency division block 130 divides the frequency of a reference clock signal CLK_REF by a predetermined division ratio to generate a first control clock signal CNT_CLK_I and a second control clock signal CNT_CLK_Q. For example, the frequency division block 130 generates the first control clock signal CNT_CLK_I by dividing the frequency of the reference clock signal CLK_REF by 2, and generates the second control clock signal CNT_CLK_Q by dividing the frequency of an inverted signal of the reference clock signal CLK_REF by 2. Herein, the first control clock signal CNT_CLK_I and the second control clock signal CNT_CLK_Q have a phase difference of approximately 90 degrees.
The pixel array 140 includes x*y pixels (not shown) arranged in column and row directions, where x and y are natural numbers corresponding to the numbers of columns and rows, respectively. The pixel array 140 sequentially outputs first to xth pixel signals VPXL1 to VPXLx by rows y times in response to the operation control signals ROW_CTRLs. In other words, the pixel array 140 outputs the first to xth pixel signals VPXL1 to VPXLx for each unit row time.
The pixel signal processing block 150 includes first to xth analog-to-digital converters ADC1 to ADCx corresponding to the respective first to xth pixel signals VPXL1 to VPXLx. The first to xth analog-to-digital converters ADC1 to ADCx generate first to xth digital signals D1<k:0> to Dx<k:0> corresponding to the first to xth pixel signals VPXL1 to VPXLx based on the ramp voltage VRAMP, the first control clock signal CNT_CLK_I and the second control clock signal CNT_CLK_Q, where k is a natural number. For example, the first to xth analog-to-digital converters ADC1 to ADCx detect voltages of the first to xth pixel signals VPXL1 to VPXLx based on the ramp voltage VRAMP, respectively, and generate the first to xth digital signals D1<k:0> to Dx<k:0> corresponding to the detection result in response to the first control clock signal CNT_CLK_I and the second control clock signal CNT_CLK_Q.
FIG. 2 is a timing diagram for describing an operation of the image sensing device 100 shown in FIG. 1. For the sake of convenience in description, FIG. 2 shows the operation of the first analog-to-digital converter ADC1 among the first to xth analog-to-digital converters ADC1 to ADCx. The operation of the first analog-to-digital converter ADC1 is representatively described below.
Referring to FIG. 2, the pixel array 140 outputs the first pixel signal VPXL1 from a pixel (not shown) corresponding to a first row and a first column during a first unit row time in response to the operation control signals ROW_CTRLs. The pixel array 140 outputs a first reset signal VPXL1_RST as the first pixel signal VPXL1 during a first reset period of the first unit row time and a first data signal VPXL1_SIG as the first pixel signal VPXL1 during a first read-out period of the first unit row time.
An operation corresponding to the first reset period is as follows. The first analog-to-digital converter ADC1 detects a voltage of the first reset signal VPXL1_RST based on the ramp voltage VRAMP. For example, the first analog-to-digital converter ADC1 generates the first digital signal D1<k:0> corresponding to a section ranging from when the ramp voltage VRAMP ramps down to when the ramp voltage VRAMP has the same level as the first reset signal VPXL1_RST. The first analog-to-digital converter ADC1 generates the first digital signal D1<k:0> based on the first control clock signal CNT_CLK_I and the second control clock signal CNT_CLK_Q having a phase difference of approximately 90 degrees.
Subsequently, the operation corresponding to the first read-out period is as follows. The first analog-to-digital converter ADC1 detects a voltage of the first data signal VPXL1_SIG based on the ramp voltage VRAMP. For example, the first analog-to-digital converter ADC1 generates the first digital signal D1<k:0> corresponding to a section ranging from when the ramp voltage VRAMP ramps down to when the ramp voltage VRAMP has the same level as the first data signal VPXL1_SIG. The first analog-to-digital converter ADC1 generates the first digital signal D1<k:0> based on the first control clock signal CNT_CLK_I and the second control clock signal CNT_CLK_Q.
Subsequently, although not illustrated in the drawings, the pixel array 140 sequentially outputs the first pixel signal VPXL1 from pixels (not shown) corresponding to second to yth rows and the first column during second to yth unit row times in response to the operation control signals ROW_CTRLs. Then, the first analog-to-digital converter ADC1 sequentially generates the first digital signal D1<k:0> during the second to yth unit row times through the same process as above.
Each of the first to xth analog-to-digital converters ADC1 to ADCx has its own offset. In other words, the image sensing device 100 has offsets for each column based on the first to xth analog-to-digital converters ADC1 to ADCx. The column offsets result in column fixed pattern noise (CFPN). To be specific, the first analog-to-digital converter ADC1 generates the first digital signal D1<k:0> in which a code offset corresponding to its offset is reflected for each unit row time. The code offset causes a miscode of the first digital signal D1<k:0>, which is a code signal. Therefore, the code offset corresponding to the offset of the first analog-to-digital converter ADC1 is reflected in the first digital signal D1<k:0>, and consequently this causes the CFPN. For example, when the first analog-to-digital converter ADC1 has a positive (+) value offset, a CFPN that is overly bright compared with other columns may occur in the first column. On the other hand, when the first analog-to-digital converter ADC1 has an offset of a negative (−) value, a CFPN that is overly dark compared with other columns may occur in the first column.
FIG. 3 is a graph for describing the concern of the image sensing device 100 shown in FIG. 1. For convenience, FIG. 3 representatively shows the first pixel signal VPXL1.
Referring to FIG. 3, a horizontal axis indicates unit row times, and a vertical axis indicates a voltage of the first pixel signal VPXL1. For convenience, the numbers 0, 1, 2, 3, 4, 5, 6, 7, . . . shown in the graph indicate the first digital signal D1<k:0> corresponding to the voltage of the first pixel signal VPXL1 as decimal numbers.
The first analog-to-digital converter ADC1 generates the first digital signal D1<k:0> corresponding to the voltage of the first pixel signal VPXL1. The first analog-to-digital converter ADC1 generates the first digital signal D1<k:0> having a consistent value based on the voltage of the first pixel signal VPXL1 for each unit row time. For example, when the first pixel signal VPXL1 having the same voltage LV1 for each unit row time is generated, the first analog-to-digital converter ADC1 may generate the first digital signal D1<k:0> corresponding to the decimal number ‘2’ for each unit row time.
The code offset corresponding to an offset Voffset of the first analog-to-digital converter ADC1 is equally reflected in the first digital signal D1<k:0> for each unit row time. Accordingly, the CFPN corresponding to the offset Voffset of the first analog-to-digital converter ADC1 occurs in the first column.